146 lines
6.7 KiB
Markdown
146 lines
6.7 KiB
Markdown
# ESP32 Specifics Reference
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> **类别：reference** | **主题：ESP32 架构深度参考 (MMU/Strapping/ADC/RTC)** | **信源：** [Espressif 官方文档](https://docs.espressif.com)
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## Table of Contents
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- [1. Hardware Architecture & Chip Families](#1-hardware-architecture--chip-families)
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- [2. Memory Management Unit (MMU) & Heap Allocation](#2-memory-management-unit-mmu--heap-allocation)
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- [3. Peripherals, Timers & Interrupts](#3-peripherals-timers--interrupts)
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- [4. Strapping Pins Deep Dive](#4-strapping-pins-deep-dive)
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- [5. ADC2/WiFi Conflict Explained](#5-adc2wifi-conflict-explained)
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- [6. Flash and PSRAM Pin Details](#6-flash-and-psram-pin-details)
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- [7. Input-Only Pins](#7-input-only-pins)
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- [8. RTC Domain and Deep Sleep](#8-rtc-domain-and-deep-sleep)
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---
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## 1. Hardware Architecture & Chip Families
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When advising on hardware selection, apply the following matrix of architectures, wireless protocols, and target use cases:
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* **ESP32 (Original):** Dual-core Xtensa LX6, 240 MHz, Wi-Fi 4, BT Classic, BLE 4.2. Best for legacy projects requiring Bluetooth Classic.
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* **ESP32-S2:** Single-core Xtensa LX7, 240 MHz, Wi-Fi 4. Best for ultra-low power and USB OTG/HID.
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* **ESP32-S3 (Performance):** Dual-core Xtensa LX7, 240 MHz, Wi-Fi 4, BLE 5.0. Features Vector instructions for AI/ML and complex GUIs.
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* **ESP32-C2:** Single-core RISC-V, 120 MHz, Wi-Fi 4, BLE 5.0. Cost-sensitive ESP8266 replacements.
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* **ESP32-C3 (Connectivity):** Single-core RISC-V, 160 MHz, Wi-Fi 4, BLE 5.0. Standard budget IoT node.
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* **ESP32-C5:** Single-core RISC-V, 240 MHz, Dual-band Wi-Fi 6 (2.4/5GHz), BLE 5, Zigbee/Thread.
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* **ESP32-C6:** Single-core RISC-V, 160 MHz, Wi-Fi 6 (2.4GHz), BLE 5.3, Zigbee/Thread. Next-gen Matter/mesh nodes.
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* **ESP32-H2 (Hub/Home):** Single-core RISC-V, 96 MHz, BLE 5.0, Zigbee/Thread. *Crucial Note: No Wi-Fi*.
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* **ESP32-P4 (Powerhouse):** Dual-core RISC-V, 400 MHz. *Crucial Note: No wireless capabilities*. Features H.264 encoding, dual MIPI, and heavy multimedia processing.
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---
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## 2. Memory Management Unit (MMU) & Heap Allocation
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Understand the complex memory hierarchy managed by the MMU:
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* **DRAM (Data RAM):** Holds standard variables and the heap. Single-byte accessible (`MALLOC_CAP_8BIT`).
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* **IRAM (Instruction RAM):** Strictly holds executable code operating at full CPU speed. Code handling interrupts or flash writes MUST reside here. Generic access requires 32-bit alignment (`MALLOC_CAP_32BIT`).
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* **D/IRAM:** Flexible RAM usable dynamically on both data and instruction buses.
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* **RTC Memory:** Fast memory runs the ULP coprocessor; Slow memory holds `RTC_DATA_ATTR` variables during Deep Sleep.
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* **PSRAM (Pseudo-Static RAM):** External/integrated RAM mapped to virtual address space for heavy workloads.
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* **Heap Allocation:** Use capabilities-based allocation: `heap_caps_malloc(size, MALLOC_CAP_DMA)` for hardware DMA, `MALLOC_CAP_SPIRAM` for external PSRAM, and `MALLOC_CAP_SIMD` for 16-byte aligned SIMD operations.
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---
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## 3. Peripherals, Timers & Interrupts
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### Timers & Watchdogs
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* **GPTimer:** In ESP-IDF v5.0+, the legacy Timer Group is deprecated and replaced by GPTimer (`gptimer.h`). Requires `gptimer_config_t` (clock source, direction, resolution). Operations include `gptimer_start()`, `stop()`, and `set_raw_count()`.
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* **Watchdog Timers:** Interrupt WDT (IWDT) monitors CPU stalls from long ISRs. Task WDT (TWDT) triggers if a task fails to yield via `vTaskDelay`.
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### Interrupt Architecture
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* **Xtensa:** Uses internal Xtensa controller (High-level assembly, Low-level C).
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* **RISC-V:** Uses standard PLIC and CLIC.
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* **Interrupt Matrix:** Maps physical hardware interrupts to specific CPU lines (Core 0 vs Core 1).
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### Specialized Peripherals & Accelerators
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* **Comm Interfaces:** I2S (digital audio/PDM), TWAI (CAN 2.0B bus), USB-OTG (S2/S3 Host/Device), USB-Serial/JTAG (C3, C6, S3, H2 direct OpenOCD debug).
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* **Motor/Lighting:** LEDC (Hardware PWM), MCPWM (Advanced BLDC driving, dead-time), PCNT (Quadrature encoders).
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* **P-Series / S-Series Accelerators:** Hardware JPEG/H.264 codecs, ISP for MIPI cameras, PPA pixel blending, GDMA engines, Crypto/TRNG accelerators for Secure Boot.
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---
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## 4. Strapping Pins Deep Dive
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ESP32 reads the state of five GPIO pins at boot to determine operating mode. These pins are safe to use for other purposes after boot completes, but their state at reset/power-on matters.
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### GPIO0 — Boot Mode Selection
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- HIGH (default)：Result=Normal execution from flash
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- LOW：Result=Download mode (firmware upload via UART)
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**Details:**
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- Has internal pull-up resistor (default HIGH)
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- Safe to use after boot for any function
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- Commonly used for: buttons, capacitive touch, general I/O
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**Warning:** If using GPIO0 as a button input, ensure it is not held LOW during reset/power-on, or the chip will enter download mode instead of running your program.
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---
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### GPIO12 (MTDI) — DANGER — Flash Voltage Selection
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- **LOW (required)**：Result=3.3V flash voltage — CORRECT for most modules
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- **HIGH**：Result=1.8V flash voltage — WILL FAIL TO BOOT on 3.3V flash modules
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**THIS IS THE MOST DANGEROUS STRAPPING PIN**
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**Safe usage patterns:**
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- Use external pull-DOWN resistor if GPIO12 must be used
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- Ensure any connected device doesn't drive HIGH during boot
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- Use `espefuse.py` to permanently set flash voltage (irreversible)
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**Recovery from "bricked" state:**
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1. Disconnect anything from GPIO12
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2. Add pull-down resistor (10kΩ to GND) if needed
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3. Hold GPIO0 LOW
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4. Power cycle the module
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5. Flash should now be accessible via esptool
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---
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## 5. ADC2/WiFi Conflict Explained
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### The Problem
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ADC2 shares internal hardware resources with the WiFi RF calibration and transmission circuits. When WiFi (or Bluetooth on original ESP32) is active, ADC2 readings are unreliable or completely invalid.
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### ADC1 Channels (Always Safe)
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ADC1 has its own dedicated hardware and works regardless of WiFi state:
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- **GPIO32-39** (Original ESP32)
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### Variants Without This Conflict
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- **ESP32-C3:** Single ADC, always available
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- **ESP32-C6:** Single ADC, always available
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---
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## 6. Flash and PSRAM Pin Details
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### SPI Flash Pins (GPIO6-11) — NEVER USE
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These pins are hardwired to the SPI flash memory chip inside the module. Using them will immediately crash the ESP32.
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### PSRAM Pins (GPIO16-17) — WROVER Only
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ESP32-WROVER modules include onboard PSRAM that uses GPIO16 and GPIO17.
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---
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## 7. Input-Only Pins
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### GPIO34, 35, 36, 39 — Hardware Limitations
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These four pins CANNOT be used for digital output, I2C, SPI MOSI/SCLK, or UART TX. They have no internal pull resistors.
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---
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## 8. RTC Domain and Deep Sleep
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### RTC GPIO Overview
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Only specific GPIOs can function during deep sleep or wake the ESP32 from deep sleep.
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**Deep Sleep Wake Sources:**
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- EXT0: Single RTC GPIO, level-triggered
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- EXT1: Multiple RTC GPIOs
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- Touch pad wake
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- ULP coprocessor
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